/**
 * Combinational logic sensitive list
 * 组合逻辑敏感列表
 *
 * Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS. 
 * This removes typo mistakes and thus avoids simulation and synthesis mismatches.
 * 
 * Verilog 2001允许我们在敏感列表中使用星号，而不是在RHS中列出所有的变量。
 * 这消除了输入错误，从而避免了模拟和合成不匹配。
 */

module star_example();

reg a, b, c, d, e;
reg [2:0] sum, sum95;

// Verilog 2k example for usage of star for combo logic
// Verilog 2k为组合逻辑使用星号的示例
always @ (*)
begin : SUM_V2K
  sum = a + b + c + d + e; 
end

// Verilog 95 example for above code
// 以上代码的Verilog 95示例
always @ (a or b or c or d or e)
begin : SUM_V95
  sum95 = a + b + c + d + e; 
end

initial begin
  $monitor ("%g a=%b b=%b c=%b d=%b e=%b sum=%b sum95=%b", 
    $time, a, b, c, d, e, sum, sum95);
  #1 a = 1;
  #1 b = 1;
  #1 c = 1;
  #1 d = 1;
  #1 e = 1;
  #1 $finish;
end

endmodule
